Why Choose Deposited Metal Contacts?
- Low contact resistance with adhesion/barrier engineering
- Clean lift-off using controlled rates and substrate temperature
- Uniform films across 100–200 mm (300 mm on request)
- Documented process: thickness, rate, base pressure, Rs (optional)
- Fast R&D lead times with production scaling available
Applications
- Ohmic and Schottky contacts on Si, SiC, GaAs, GaN, InP
- Bond pads & interconnects for MEMS/CMOS packaging
- Seed layers for Cu/Ni/Au electroplating
- Barrier stacks for diffusion and electromigration control
Typical Stacks
- Adhesion + Au: Ti/Au, Cr/Au
- Al-based ohmic: Ti/Al/Ni/Au
- Schottky: Ni/Au, Pt/Au
- Barrier: Ti/Pt/Au, Ti/W/Au
Process Window
- Thickness: 5 nm – 3 µm (±3–5% uniformity)
- Rates: 0.5–3 Å/s (lift-off), up to 10 Å/s (blanket)
- Base pressure: ≤ 1×10⁻⁶ Torr
- Substrate temperature: RT–250 °C
Substrates
- Silicon (CZ, FZ, SOI), SiC, GaAs, GaN/Si, InP
- Glass (BK7, Borofloat 33, D263, fused silica, ITO)
- Sapphire, quartz, LiNbO₃
Low-defect, lift-off-compatible metal layers deposited under UHV conditions. Perfect for MEMS, RF, and power devices.
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Deposited Metal Contacts (AR Ion & Thermal/E-Beam Evaporation)
We deposit high-purity metal films for ohmic and Schottky contacts on silicon, compound semiconductors, glass, quartz, and sapphire. Processes are optimized for clean lift-off, excellent adhesion, and low contact resistance with precise thickness control.

Typical Stacks & Use Cases
- Adhesion + Au: Ti/Au, Cr/Au for bond pads, interconnects, wire-bonding
- Low-resistivity Al-based: Ti/Al/Ni/Au for Si/SiC ohmic contacts
- Schottky contacts: Ni/Au, Pt/Au for detectors and diodes
- Barrier stacks: Ti/Pt/Au or Ti/W/Au for diffusion and electromigration control
- Seed layers for subsequent electroplating (Cu, Ni, Au)
Process Capabilities
- Methods: AR ion cleaning, thermal & e-beam evaporation (multi-pocket)
- Thickness: ~5 nm to ~2 µm (stack-dependent)
- Uniformity: ±3–8% typical across 100–200 mm; 300 mm on request
- Rates: Lift-off-friendly low rates for fine features; higher rates for blanket metal
- Adhesion prep: in-situ AR ion mill/etch for native oxide removal
- Stress control: tuned by rate, power, and substrate temperature
Design for Fabrication
- Lift-off: undercut resists (e.g., bilayer) recommended for ≥300 nm Au
- Lines/Spaces: successful down to sub-micron with controlled rates and angles
- Step coverage: evaporation is directional; consider angled deposit or thicker adhesion layer
- Anneals: optional RTA/furnace steps for ohmic formation (stack-specific)
Substrates We Support
- Si (CZ, FZ, SOI), SiC, GaAs, GaN/Si, InP
- Glass: fused silica, BK7, Borofloat, D263, ITO-coated glass
- Sapphire and quartz single crystal
Metrology & Documentation
- Thickness by QCM/ellipsometry/profilometry (as applicable)
- Sheet resistance (Rs) for conductive stacks
- Adhesion & visual inspection; microscope photos on request
FAQs
Can you do lift-off? Yes—rates and substrate temperature are tuned for clean lift-off.
What metal purity? 99.99%–99.999% sources depending on metal.
Do you offer patterned contacts? Yes—use your mask & resist process; we handle the deposition.
Learn more about substrates: Silicon, SiC, GaAs, Fused Silica, Sapphire.
Deposited Metal Contacts (AR Ion, E-Beam, and Thermal Evaporation)
UniversityWafer provides precision metal contact deposition services for semiconductor, MEMS, and photonic device fabrication. We specialize in ohmic and Schottky contact formation using high-purity metal evaporation in ultra-high-vacuum (UHV) systems equipped with AR ion cleaning, multi-pocket e-beam sources, and quartz crystal monitoring for exact film thickness control.
Purpose and Applications
Deposited metal contacts provide the electrical interface between device layers and the external circuit. High-quality metallization ensures low contact resistance, thermal stability, and excellent adhesion—critical for power electronics, RF devices, sensors, and optoelectronic components.
- Silicon & SiC ohmic contacts for diodes and transistors
- GaAs/GaN Schottky contacts for detectors and HEMTs
- Bond pads and interconnects for MEMS or CMOS packaging
- Seed and barrier layers for electroplating and diffusion control
Available Metals and Stack Options
- Gold-based: Ti/Au, Cr/Au, Ni/Au for low-resistance pads
- Aluminum-based: Ti/Al/Ni/Au for Si, SiC, GaN devices
- Barrier stacks: Ti/Pt/Au, Ti/W/Au for thermal stability
- Specialty metals: Ag, Mo, Ta, W, Pd, Pt, Cu, Ni, Co
- Custom multi-layer sequences available upon request
Deposition Techniques
- Thermal Evaporation: gentle heating for low-melting metals (Al, Ag)
- E-Beam Evaporation: high precision, dense films, ideal for noble metals
- AR Ion Cleaning: pre-deposition surface activation and oxide removal
- In-Situ Layer Stacking: sequential metal deposition without vacuum break
- In-situ Ar-ion cleaning inside the evaporator: Removes native oxides directly within the deposition chamber before metal evaporation, ensuring pristine interfaces and improved adhesion.
Film & Process Specifications
- Thickness range: 5 nm – 3 µm (±3–5% uniformity across 100–200 mm)
- Deposition rates: 0.5–3 Å/s for lift-off, up to 10 Å/s for blanket coating
- Vacuum level: ≤ 1×10⁻⁶ Torr base pressure
- Substrate size: 100–200 mm standard; 300 mm optional
- Substrate temperature: RT–250 °C (controlled)
Metrology & Quality Control
- Thickness verification via profilometer or ellipsometer
- Sheet resistance (Rs) mapping for conductive films
- Surface morphology and grain analysis (optical microscopy)
- Optional SEM or AFM for research documentation
Post-Deposition Processing
- Lift-off compatible process with controlled rate and angle
- RTA or furnace annealing for ohmic contact formation
- Wire-bonding tests and visual inspection on request
Substrates Supported
- Silicon (CZ, FZ, SOI), SiC, GaAs, GaN/Si, InP
- Glass: BK7, Borofloat 33, D263, fused silica, ITO glass
- Sapphire, quartz, and LiNbO₃ for photonic components
Advantages of AR Ion & E-Beam Evaporated Contacts
- Superior adhesion and purity due to in-situ pre-cleaning
- High density and smoothness for low-resistance interfaces
- Controlled stoichiometry and reproducible layer thickness
- Low contamination and film stress
Documentation and Lead Times
Each run includes detailed process records: base pressure, deposition rate, metal source batch, and substrate ID. Standard turnaround is 3–5 business days for R&D lots; production scaling available.
Related services: Metal Deposition | Silicon Wafers | Sapphire Wafers | SiC Substrates.