Small Quantity Metal Deposition
An applied physics researcher requested the following quote:
I’m looking for quotes for some metal deposition on undoped Si wafers (listed below). Please include available process options. The Cr/Ti would be used as an adhesion layer.
- 5 nm Cr, 500 nm Au
- 5 nm Cr, 500 nm Cu
- 5 nm Ti, 500 nm Au
Build better devices with precision-controlled metal coatings—ready for MEMS, sensors, and photonic applications.
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Metal Thin-Film Deposition Overview
Metal deposition is a fundamental process in semiconductor fabrication, thin-film optics, and MEMS engineering. It involves transferring conductive or reflective metallic layers onto polished substrates with nanometer-scale control. UniversityWafer provides customized deposition for research, prototyping, and small-batch production, supporting metals such as gold, aluminum, copper, nickel, and platinum.
Applications in Research and Industry
- Semiconductors: Contact pads, interconnects, and gate electrodes for devices and test structures.
- Optoelectronics: Mirror coatings, optical filters, and reflective sensors for NIR and visible ranges.
- MEMS and Sensors: Electrodes, heater elements, and mass-sensitive resonators.
- Photonics: Metal layers for plasmonic and metamaterial structures.
- Energy Systems: Metallic back contacts for photovoltaic wafers and thermoelectric devices.
Deposition Methods Explained
Each technique offers unique advantages depending on thickness, purity, and adhesion requirements:
- E-beam evaporation: Uses high-energy electrons to vaporize metal targets in high vacuum, producing ultra-pure dense films.
- Thermal evaporation: Cost-efficient method for metals with moderate melting points such as Al and Cu.
- DC/RF Magnetron sputtering: Provides excellent step coverage, adhesion, and repeatability across large wafers.
- Ion-assisted and reactive sputtering: Enables nitrides like TiN for barrier or optical applications.
Controlling Thickness and Uniformity
Uniformity and film thickness directly affect electrical conductivity and optical properties. UniversityWafer achieves precision through calibrated deposition rates and wafer rotation during processing. Typical tolerances range from ±3% to ±8%, with surface roughness below 1 nm RMS achievable for noble metals like gold and platinum.
Substrate Compatibility
Deposition services are available for a wide range of substrates including:
- Silicon (CZ/FZ, SSP/DSP)
- Silicon-on-Insulator (SOI)
- Sapphire and Fused Quartz
- Silicon Carbide (SiC), Gallium Arsenide (GaAs), and InP
Surface Preparation & Cleanroom Quality
Before deposition, wafers are cleaned using solvent rinses and oxygen plasma treatments to remove organic residues. This ensures excellent adhesion between the substrate and metal film. All processes are carried out in cleanroom environments to maintain optical and semiconductor-grade surface quality.
Advantages of UniversityWafer Services
- High-vacuum systems (≤10-6 Torr base pressure)
- Fast turnaround and process documentation
- Custom metal stacks and adhesion layers
- Wafer-level thickness mapping and verification
- Integration with photolithography and optical coating workflows
Request a Custom Quote
Provide your desired metal combination, substrate size, and target thickness. Our engineers will recommend the most suitable deposition process and send a detailed quotation.
Why Choose Our Metal Deposition
- R&D-friendly lead times with process recommendations
- Lift-off compatible rates and stack guidance
- Uniformity control for 100–200 mm (300 mm on request)
- Documentation: thickness, Rs, and microscopy on request
Typical Use Cases
- MEMS electrodes, interconnects, and ground planes
- Photonic and optical mirrors, absorbers, and coatings
- Sensor metallization and bonding pads
- Microfluidic seed layers and conductive frames
Common Stack Recipes
- Adhesion + Noble Metal: Ti/Au or Cr/Au
- Low-Resistivity Conductors: Al, Cu
- Hard/Stable Layers: Ni, Pt, W, Mo
- Nitrides (reactive sputter): TiN for optical or barrier use
Thickness & Rate Guide (Typical)
| Metal/Layer | Typical Thickness | Notes |
|---|---|---|
| Ti or Cr (adhesion) | 5–30 nm | Choose by substrate & stress target |
| Au | 50 nm – 2 µm | E-beam (dense), lift-off tuned rates |
| Al | 50 nm – 1 µm | Sputter for step coverage; evap for speed |
| Cu / Ni / Pt | 30 nm – 1 µm | Contact layers & barriers; verify Rs |
| TiN | 10–200 nm | Reactive sputter; optical/electrical barriers |
Lift-Off Design Tips
- Resist thickness ≥ 2–3× metal thickness
- Use undercut profiles for clean edges
- Limit substrate heating during deposition
- Include target CD and step height in RFQ
Surface Prep & Cleanliness
- Solvent clean + O2 plasma descum when required
- In-situ plasma or ion clean to enhance adhesion
- Low-particle workflow for optical & device-grade wafers
Supported Substrates
- Silicon wafers (CZ/FZ, SSP/DSP)
- SOI, Sapphire, Fused Quartz/Glass
- SiC, GaAs, and InP (on request)
Related Services
Adhesion Layer Selection (Ti vs. Cr)
- Ti (5–20 nm): Excellent on Si/SiO2 and many dielectrics; slightly lower optical absorption than Cr in VIS; good for Au lift-off.
- Cr (3–15 nm): Very strong adhesion to glass/quartz; higher stress and optical loss than Ti; commonly used for Au/Cu seed layers.
- Rule of thumb: Start with 5–10 nm, increase only if tape/sonication tests fail or if rough surfaces require more anchoring.
Electrical Targets & Sheet Resistance
We can tune thickness for your target sheet resistance (Rs) and skin-depth requirements. Contact us for cryogenic or RF constraints.
| Material | Example Thickness | Typical Rs (Ω/□) | Notes |
|---|---|---|---|
| Au (with 5–10 nm Ti/Cr) | 100 nm | ~0.3–0.6 | Low resistivity, lift-off friendly rates; avoid sulfur contamination. |
| Al | 200 nm | ~0.4–0.8 | Good for interconnects; sputter for step coverage. |
| Cu (with 5–10 nm Cr) | 200 nm | ~0.2–0.5 | Great conductivity; consider barrier if later plating or diffusion is expected. |
| Pt | 100 nm | ~1.0–2.0 | Chemically robust; good for high-temp or bio interfaces. |
Film Stress & Thermal Budget
- Stress control: Adjust power, pressure, and rate; select e-beam vs. sputter based on stack and substrate tolerance.
- Annealing: Optional post-deposition anneals (e.g., 150–350 °C in N2/vacuum) to relieve stress or lower Rs on Au/Al/Cu.
- CTE mismatch: Large metal areas on thin wafers may bow—share thickness maps or target bow specs in your RFQ.
Diffusion Barriers & Seed Layers
- Barriers: TiN, Cr, W, or Pt to mitigate Cu/Au diffusion into SiO2/polymers.
- Seeds for plating: 10–50 nm Cu or Ni as an electroplating base; verify via continuity test structures.
- Stack examples: Cr/Cu/Au for wire-bond pads; Ti/Pt/Au for robust, high-temp pads.
Feature Coverage & Lift-Off Windows
- Lift-off: Resist ≥2–3× metal thickness; use undercut profiles for edges & vias.
- Step coverage: Prefer sputtering for conformality over topography; evaporation is more directional.
- Narrow gaps: Reduce rate/temperature and consider two-step deposition (adhesion + bulk) to avoid fence formation.
Uniformity & Wafer Sizes
- 100–150 mm wafers: ±3–6% typical, stack-dependent.
- 200 mm wafers: ±4–8% typical with rotation and tuning.
- 300 mm: Available on request—share exact uniformity map specs.
Metrology & Documentation
- Thickness: QCM-calibrated, ellipsometry/reflectometry on witness.
- Electrical: 4-point probe Rs mapping (on coupons or wafers).
- Surface: Optical/SEM micrographs on request; AFM for roughness studies.
Handling, Packaging & Cleanliness
- Wafers packaged in clean cassettes or single-wafer shippers.
- Gold is soft—store with spacers, avoid shear contact; wear gloves.
- Provide any contamination-control requirements (e.g., no Cl-based chemistries).
Order Checklist (Include with RFQ)
- Substrate: material, diameter, thickness, orientation, polish (SSP/DSP).
- Stack: order, each thickness (e.g., 5 nm Ti / 500 nm Au).
- Process: evaporation vs. sputtering; lift-off vs. blanket + etch; anneal yes/no.
- Targets: Rs, roughness, uniformity, max wafer temperature.
- Quantities, delivery date, and any inspection docs required.
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