What is the silicon lattice constant at room temperature?

At ~300 K, the silicon lattice constant a ≈ 5.431 Å (0.5431 nm) for the diamond cubic structure.

Does wafer orientation change the lattice constant?

No. Orientation ((100), (111), (110)) is the cut relative to the cubic cell. The lattice parameter a is a bulk constant; orientation affects surface atomic arrangement and step/terrace geometry, not a.

How does temperature affect the lattice parameter?

a increases slightly with temperature due to thermal expansion. Engineering models use a(T)=a0·(1+αΔT+…); for modest ΔT the change is small but relevant for precision epitaxy/metrology.

How do I estimate lattice mismatch for epitaxy?

Use f=(a_film−a_substrate)/a_substrate. Example: GaAs on Si has ~(+4.1%) mismatch; 3C-SiC on Si is ~(−19.7%). Buffer layers or compliant substrates are used to manage mismatch.

Silicon Lattice Constant (a = 5.431 Å at 300 K) — Orientation, Mismatch & Wafer Notes

Customer Inquiry: Epi Silicon and GaAs on Glass

Inquiry:
We are looking for glass substrates (2″ or 3″) with an epitaxial Si layer (thickness ~400 nm). I was wondering if this can be customized?

After considering further, it seems it might not be feasible to grow or deposit an epitaxial silicon layer directly on a glass substrate due to the lattice mismatch and other thermal/structural limitations.

Following additional discussion with my colleague, it appears that we only need to deposit a layer of amorphous silicon (a-Si) instead of epitaxial Si, due to its lower optical loss.

We would also like to check for another project: we are considering a layer of single-crystalline, undoped epitaxial GaAs (thickness ≈ 360 nm) on a fused-silica substrate (3″ or 4″). Would UniversityWafer be able to provide this, or should we request an MBE/MOCVD grower to perform the epilayer growth on a GaAs substrate and then conduct the wafer bonding ourselves?

UniversityWafer, Inc. Response:

“Let's try. Send us all your specs.”

Reference: #270980 for the result.

Design low-loss optical substrates with amorphous Si or bonded GaAs layers on fused silica. Buy now!

Get Your Quote FAST! Or, Buy Online and Start Researching Today!

Silicon Lattice

The silicon lattice constant defines the cubic unit cell dimension of crystalline Si — a foundation for understanding strain, mismatch, and epitaxial design. At 300 K, a = 5.431 Å. Knowing this value and its temperature dependence is critical for semiconductor device fabrication, wafer bonding, and heteroepitaxy on GaAs, SiGe, SiC, and GaN.

Did You Know?

The Si lattice expands only about 0.01 % per 40 °C rise in temperature.
GaAs is about 4 % larger than Si — creating tensile strain in heteroepitaxy.
SiGe alloys tune lattice spacing between pure Si and Ge for strain engineering.

Quick Reference

Structure: Diamond cubic (Fd-3m)
Lattice Constant (300 K): 5.431 Å (0.5431 nm)
Thermal Expansion: ≈ 2.6 × 10⁻⁶ K⁻¹
Density: 2.329 g/cm³
Bandgap: 1.12 eV (indirect)

Applications

Designing strain-balanced SiGe devices
Predicting GaN-on-Si mismatch and wafer bow
Modeling SiC or sapphire heterointegration
Optimizing crystal orientation for MEMS and photonics

Request a Quote

Need high-purity or orientation-controlled Si wafers for lattice or epitaxial research? Request a Silicon Wafer Quote →

Silicon Lattice Constant

Silicon (Si) crystallizes in the diamond-cubic structure. The conventional cubic cell edge—its lattice constant—is a ≈ 5.431 Å (0.5431 nm) at 300 K. This parameter underpins interplanar spacing, diffraction, strain calculations, and lattice-mismatch estimates for heteroepitaxy.

Side-by-side diagram comparing epitaxial silicon on a substrate versus amorphous silicon on a substrate

Key Conversions

1 Å = 0.1 nm = 1×10⁻¹⁰ m
Si a(300 K) ≈ 5.431 Å → 0.5431 nm → 5.431×10⁻¹⁰ m

Orientation & Planes

Wafer orientations (100), (111), and (110) describe the cut of the surface relative to the cubic axes; they do not change the bulk lattice constant. Orientation impacts surface atom density, oxide growth behavior, etch anisotropy, and device layout (flats/notches, miscut for step flow, etc.).

(100): CMOS standard; square symmetry; convenient for lithography and oxidation.
(111): Close-packed; used in MEMS and III–V/Si integration studies.
(110): Useful for mobility/channel engineering and some MEMS etch geometries.

Temperature Dependence

The lattice parameter a increases slightly with temperature due to thermal expansion. Around room temperature, the CTE is on the order of ~2.6×10⁻⁶ K⁻¹ (rising with T). For routine engineering, use a 300 K reference and apply a linear or tabulated CTE over your range; for precision epitaxy/metrology, specify the measurement temperature.

Interplanar Spacing & Bragg Example

For cubic crystals, interplanar spacing is d_hkl = a / √(h²+k²+l²). Bragg’s law: nλ = 2 d sin θ.

Si Reflection	d_hkl (Å)	2θ (Cu Kα, 1.5406 Å)	Note
(111)	5.431/√3 ≈ 3.135	≈ 28.4°	Strong fundamental
(220)	5.431/√8 ≈ 1.920	≈ 47.3°	Allowed in diamond-cubic
(311)	5.431/√11 ≈ 1.638	≈ 56.2°	Allowed
(400)	5.431/4 ≈ 1.358	≈ 69.0°	Allowed

Selection rules: Silicon’s diamond-cubic (two-atom basis on fcc) exhibits systematic absences. Reflections like (100), (110), (210), etc., are forbidden; strong peaks include 111, 220, 311, 400, 331, 422….

SiGe Lattice (Vegard) & Strain

For Si_1−xGe_x, an engineering estimate uses Vegard’s law: a(x) ≈ (1−x)a_Si + x a_Ge (with a small bowing correction in precision work). Example: at x=0.20, a ≈ 0.8·5.431 + 0.2·5.658 ≈ 5.476 Å → mismatch to Si ≈ (5.476−5.431)/5.431 ≈ +0.83%.

Thin SiGe on Si remains pseudomorphic (strained) below a critical thickness; above it, relaxation introduces misfit dislocations. Use a critical-thickness model (e.g., Matthews–Blakeslee) in process planning, and verify with HRXRD/RSM.

Lattice Mismatch Examples (to Si)

Approximate comparisons at ~300 K using f=(a_film−a_Si)/a_Si:

Material	Lattice Constant (Å)	Mismatch to Si	Notes
GaAs (zinc blende)	~5.653	≈ +4.1%	Buffers/compliant layers required
Ge (diamond)	~5.658	≈ +4.2%	Graded SiGe buffers common
InP (zinc blende)	~5.869	≈ +8.1%	Large tensile mismatch vs Si
3C-SiC (zinc blende)	~4.359	≈ −19.7%	Large compressive mismatch
GaN (wurtzite, a_hex)	~3.189 (hex)	Anisotropic	GaN-on-Si uses engineered buffer stacks

Exact values depend on temperature, composition (alloys), and phase.

Practical Wafer Ordering Notes

Orientation tolerance: Typical spec ±0.5° (tighter on request). Miscut (e.g., 2–4° toward <110>) can aid step-flow epitaxy.
Diameter & flats/notches: Conform to SEMI standards for 100–300 mm; indicate primary/secondary flat orientation if needed.
Resistivity & type: CZ or FZ, p/n, and target ρ influence contamination and device behavior.
Surface: SSP/DSP, epi-ready polish, oxide/nitride capping if required for handling.
Metrology: Ask for XRD/RSM and thickness/roughness data if you plan lattice-sensitive epitaxy.

Metrology Notes

HRXRD: lattice parameter, strain/relaxation, reciprocal-space maps for tilted/strained layers.
Ellipsometry & AFM: thickness/roughness to support XRD modeling.
TEM/EDS (advanced): interface quality and defect analysis in heteroepitaxy.

What is Silicon Lattice Constant?