SiC Manufacturing 101 — Wafers, Polytypes, and Processing
From high-purity powders and crystal growth to CMP and metrology—what makes silicon carbide wafers different and how to choose them for power and RF.
1) Why SiC instead of Silicon?
- Wide bandgap (4H ~3.26 eV): Operates at higher T/V with lower leakage.
- ~10× breakdown field: Thinner drift layers → lower RDS(on), higher efficiency.
- High thermal conductivity (~370 W/m·K): Better heat removal, lighter cooling.
2) Polytypes & diameter roadmap
4H-SiC dominates power devices; 6H-SiC is niche; 3C-SiC remains R&D. Commercial wafer sizes are 100/150 mm with a strong push to 200 mm for capacity and cost structure.
3) Raw materials & purification
- Ultra-pure Si & C sources (6N–7N), dopants (N/P for n-type, Al/B for p-type)
- Chemical cleaning (acid leach), thermal conditioning, particle size control
4) Crystal growth (PVT, CF-PVT, HTCVD)
PVT (modified Lely) sublimates high-purity SiC powder & re-crystallizes on a seed (polytype-defining) above 2000 °C in Ar. CF-PVT extends runs with continuous feed (enables larger diameters). HTCVD deposits from gases (silane/propane) with tighter dopant/defect control, at lower growth rates.
5) Ingot prep & wafering
- Orientation: XRD alignment; 4° off-axis common for 4H epi.
- Shaping: Diamond grinding to target OD, remove outer defects.
- Slicing: Diamond multi-wire; slow to minimize kerf & subsurface damage.
- Edges: Bevel + polish to reduce stress cracks/chipping.
6) Surface finishing
- Lapping: Remove saw damage, improve parallelism.
- CMP: Diamond/oxidizer slurries; multi-stage down to <1 nm RMS.
- Chemical etch: Molten KOH or RIE to reveal/remove latent damage.
7) Defect control & QC
- Structural: X-ray topography (micropipes, dislocations), EBSD.
- Surface: AFM, optical profilometry, automated optical inspection.
- Electrical: 4-pt resistivity map, Hall (μ, carriers), lifetime (µ-PCD/PL).
- Chemical: SIMS/GDMS for trace elements, dopant profiles.
8) Spec’ing wafers for your flow
- Choose polytype & off-axis (e.g., 4H, 4° off) aligned with epi requirements.
- Set conductivity (n/p), target resistivity, epi thickness/grade if needed.
- Define diameter, thickness, TTV, bow/warp, and edge profile.
- Call out metrology (AFM RMS, micropipe/dislocation limits, lifetime minimums).
- Packaging/cleanliness: metal-ion & particle specs, certified carriers.
9) Applications & what to expect
- Power: EV traction inverters, OBC/DC-DC, PV/wind inverters, drives (efficiency ↑, cooling ↓).
- RF/Microwave: 5G base stations, radar; high power density and stability.
- Harsh environments: High-T sensors, nuclear/aerospace where Si fails.
10) Buying tips
- Ask for current defect maps and lifetime data with each lot.
- Confirm epi readiness (front CMP target, haze/particles) and edge specs.
- For scaleup: validate 200 mm supply, epi tool compatibility, and carrier/FOUP fit.